1. Field of the Invention
The present invention relates to a configuration of a high frequency DRAM module, and more particularly to a memory module device for use in a high-frequency operation.
2. Description of the Related Art
In electronic data processing (EDP) systems such as a personal computer (PC), a work station, a server etc., a memory device that is a main memory is commonly configured in a module in which a plurality of DRAMs are connected with one another via a system bus. To increase the overall efficiency of the EDP system, data transfer between the memory module and a system chip set, for example a CPU etc., must occur at a higher speed.
Referring first to FIG. 1, which illustrates a block diagram of a conventional DRAM module, each of bilateral data buses (hereinafter, referred to as “DQ bus”) is connected directly to each of plural DRAMs 10–17 through a connector, and a command-address bus (hereinafter, referred to as “CA bus”) is connected to each of the DRAMs 10–17 equipped in the module 50 through a register 20. A memory system employing such a module has a problem in achieving greater than a 600 Mbps/pin data rate in the event that operating frequency is dictated by a 300 MHz dual edge clock, because of the “stub” connection configuration of the respective DQ buses.
To improve this limitation on the operation frequency, referring to FIG. 2, module devices 100, 200 utilize respective buffers 40, 42, 44, 46 for the DQ buses. As shown in FIG. 2, in each DQ buffer 40, 42, 44, 46, two ports PO1, PO2 are allocated to single data, and the single data input through any one of the two ports is re-driven to another port. Further, through one port, input data is transferred to the DRAM or the data output from the DRAM is externally transferred. In such a memory system in which a DRAM module is used and equipped with buffers, all data buses have a “point-to-point” configuration. Thus, these systems enjoy data transfer rates that can be increased up to several gigahertz (GHz).
However, although data operating frequency is increased in the configuration of FIG. 2, the difference in operating frequency between the data DQ and command address CA lines becomes large because the bus structure of the CA line s still in a “stub” configuration. Furthermore, a phase difference is generated, since structures of the data bus DQ and the command address CA bus are different from each other. Further, since a register and a buffer having each of process operations are independent of each other, it is difficult to achieve synchronization between the command address bus CA and the data bus DQ.